The present invention relates generally to integrated circuits and relates more specifically to metal patterning processes for use in manufacturing integrated circuits.
Integrated circuits (ICs) commonly use copper interconnects (or “lines”) to connect transistors and other semiconductor devices on the ICs. These interconnects are typically fabricated using an additive damascene process in which an underlying insulating layer (e.g., silicon oxide) is patterned with open trenches. FIG. 1, for example, is a schematic diagram illustrating a trench 100 that may be formed in the insulating layer during IC fabrication. A subsequent deposition of copper on the insulating layer fills the trenches with copper. The copper is removed to the top of the insulating layer, but remains within the trenches to form a patterned conductor. Successive layers of insulator and copper are formed according to this damascene process, resulting in a multilayer copper interconnect structure.
Conventional damascene processing such as that described above is not always compatible with the trend toward smaller feature sizes in modern complementary metal-oxide-semiconductor (CMOS) technology. For instance, modern CMOS technology may require lines having widths of less than forty nanometers and aspect ratios (i.e., line width:line height) of approximately 1:2. Attempting conventional damascene processing within these parameters often results in poor liner/seed coverage on the walls of the trenches (e.g., as illustrated at 102 in FIG. 1), pinch off at the mouths of the trenches (e.g., as illustrated at 104), and reentrant reactive ion etching profiles (e.g., as illustrated at 106). Consequently, the copper filling the trenches is subject to voids, defects, and poor adhesion to the trench liners. Moreover, as the lines narrow in size, the resistivity of the copper is increased (due to, for example, the thickness of the liner relative to the thickness of the copper, the small copper grain size, and copper grain boundary and surface scattering phenomena), resulting in decreased IC performance. In addition, it is difficult to obtain fine-pitch line-space structures (e.g., sixty nanometers or less) using conventional direct lithography processes on copper.